There are two basic techniques used in digital-to-analog converters (DACs). These are the sigma-delta technique and the resistive or capacitive divider techniques. The sigma-delta technique is attractive because it achieves high resolution by precise timing instead of precisely-matched on-chip components such as resistors. In addition, the expertise needed to produce thin-film, laser-trimmed analog components is difficult to obtain; whereas, high-speed digital switching capability is commonplace in the semiconductor industry.
A basic sigma-delta DAC receives a digital signal which is summed with inverse feedback of the analog output signal (after being reconverted to a digital signal) to provide an error signal. The error signal is then processed through an integrator and a comparator to provide the analog output signal. The analog signal is also processed through an analog-to-digital converter (ADC) to provide the feedback signal.
The digital output data stream of the sigma-delta modulator must be buffered before being provided externally. If a one-bit sigma-delta modulator is used, then the buffered output signal is the output signal of the DAC. If a multi-bit sigma-delta modulator is used, then each bit must be buffered and then weighted proportionally to its significance.
A problem arises in buffering these signals using conventional technology. The buffer includes a series of inverters, each having progressively larger transistors. For example, in CMOS technology, each inverter stage includes a P-channel transistor connected in series with an N-channel transistor between positive and negative power supply voltage terminals. Because the transfer characteristics of P-channel and N-channel transistors are somewhat different, each inverter stage produces a different delay on one transition than on the other transition. This characteristic produces even-order distortion. Since N-type silicon has a higher conductance than P-type silicon, the N-channel transistor will switch faster than a similarly-sized P-channel transistor. Thus, when presented with a square wave at its input, the inverter will provide an output that has longer low pulses than high pulses. This results in a negative DC offset providing even-order (an order of zero in a Fourier expansion) distortion. While it is possible to alter the sizes of the devices to compensate for the difference in the switching speeds, the compensation will be inexact as temperature, voltage, and processing parameters vary. Thus, the distortion remains.
One way to compensate for the even-order distortion problem is for the DAC to provide differential outputs. Then, the differential outputs can be processed through separate smoothing filters and provided as inputs to a differential amplifier, all located off-chip. Since the distortion occurs in opposite directions between the true and complement output signals, the differential amplifier is able to cancel them out. However, cancellation through use of differential outputs would require an extra smoothing filter for the negative signal. Furthermore, this cancellation is not perfect, and is limited to the matching of the components in the smoothing filter and the amplifier.